Technical FAQ: AI Infrastructure & Semiconductor Testing
Q1: How does Shenzhen Hongda solve thermal dissipation challenges for AI Servers with 1000W+ TDP GPUs?
Answer: We utilize high-performance thermal management solutions including 9.0 W/m.K Metal Core PCBs (MCPCB) and embedded Copper Coin technology. For next-generation liquid-cooled AI clusters, we provide specialized Heavy Copper circuits (up to 20oz) that minimize resistive heating and maximize heat transfer efficiency to cold plates, ensuring stable performance for Blackwell and Rubin-class architectures.
Q2: What is your capability for maintaining 224Gbps signal integrity in high-density AI backplanes?
Answer: To support 224Gbps data rates, we employ Ultra-Low Loss (ULL) substrates such as Megtron 8 or Tachyon 100G. Our manufacturing process incorporates advanced Back-Drilling with residual stub control of <0.2mm and the use of VLP2 (Very Low Profile) copper foil to mitigate skin effect losses and jitter in high-frequency signal paths.
Q3: How do you ensure the mechanical and electrical durability of Semiconductor Load Boards?
Answer: Our semiconductor test boards are engineered with Hard Gold Plating (30-50u”) and high-Tg, low-CTE materials to withstand millions of pogo-pin insertions. We guarantee a global surface flatness of ≤0.05mm and utilize Any-layer HDI stack-ups to provide the high-density routing required for the latest SoC and AI chip verification.
Q4: Can you manufacture IC Substrates using mSAP for advanced Chiplet packaging?
Answer: Yes. Our mSAP (Modified Semi-Additive Process) production lines are capable of achieving ultra-fine line/space widths down to 15μm/15μm. This level of precision is essential for 2.5D/3D packaging and Chiplet interconnects, providing the tight registration and vertical trace profiles that traditional subtractive etching cannot deliver.
Q5: What advantages does your 120-layer capability provide for 6G and AI networking infrastructure?
Answer: Our 120-layer ultra-high-count capability allows for extreme routing density in 800G/1.6T switches and massive MIMO base stations. By integrating laser micro-vias and sophisticated registration control, we can reduce total PCB thickness while increasing interconnect density by up to 400%, enabling more complex functionality within a smaller hardware footprint.